Pipelining and Superscalar Architecture
What comes to mind when you read the twin terms pipelining and superscalar architecture? Well, if you are waist-deep into computing, you wouldn’t have to think it too hard, would you? Lets for once assume you’re an amateur. This is what this article is all about. Albert Einstein equates knowledge of a concept with the ability to explain it to a six-year-old right? Here is what it all means.
A lot of work goes into making a computer to execute multiple instructions given to it by the user or operator. As simple as it seems on the surface, lots of operations are being executed behind the scenes. One that users may never know. Sometimes, this complex operation would require the use of multiple hardware.
Pipelining, simply, refers to an implementation technique in which multiple instructions overlay each other in execution. Normally, this would take extra hardware to pull off, but pipelining allows for the use of no additional hardware. If anything, it only allows different parts of the hardware to function for different instructions all at the same time. Pipelining, among other things, increases the speed in computer programs.
Superscalar architecture, on the other hand, allows for several instructions to be initiated simultaneously but executed independently. Let’s take a closer look at each.
In the field of computer science, pipelining refers to a procedure for breaking down a sequential process into sub-processes. That is, pipelining engages every part of the computer processor with instructions by distributing inbound instructions into a sequence that is performed by various parts of the processor unit, in a parallel manner. Hence, the name “pipeline”.
In pipelining, each sub-process is executed in a special section that operates simultaneously with all other sections. Picture it like a soap making plant. With each stage coming after the other. Like the soaps in a factory moving through a channel, pipelining is a collection of processing sections allowing smooth passage for the flow of binary information.
Like the soaps in the assembly line, each section has something to add to the manufacturing process. Similarly, each section in the CPU (central processing unit) does the task apportioned to it. The outcome gotten from the computation in each section is then transmitted to the next section in the pipeline. The ultimate result comes out after the data have successfully run through all sections.
Therefore, the name “pipeline” refers to a flow of information similar to that of an assembly line. It refers to pipelines or networks through which several computations can be carried out at the same time but in distinct segments.
Superscalar architecture, on the other hand, refers to a method of parallel computing. In this kind of design, the computer’s CPU coordinates multiple instruction pipelines at the same time. The operation allows the execution of several instructions simultaneously. It does so by supplying the various pipelines with instructions.
If you must execute a superscalar architecture, then the instruction-capturing mechanism of your computer must be so designed to retrieve and designate instructions intelligently. Else, stalls could become a normal occurrence.
Again, picture the soap manufacturing plant we referred to earlier. For instance, a soap plant consists of chambers A, B, and C. Soap batches can only move in one direction, from A, B, and C.
Also, it takes equal time to go through each phase. If chamber B, represents packaging, and it can contain only handle nine bars of soaps at a time and there are also three packaging machines in that chamber, each of which can work on three bars of soaps.
If it works at optimum condition, the packaging section can handle three bars of soaps at a time. It then sends out nine and immediately packages another three bars of soap. Although the packaging machines can handle only three bars at a time, because there are three of them in operation, they would be empty by a new set arrives.
The sequence the nine soaps take is similar to instructions flowing through the clock cycle of a computer’s CPU. Chamber A represents the instruction-capturing mechanism. Chamber B represents the execution units, and Chamber C represents the final results. These final results are then captured in registers or caches.
Superscalar architecture is a design that allows for the execution of more than one instruction during a single clock cycle. In this kind of design, the instruction-capturing mechanism retrieves and intelligently decides whether an instruction can be executed separately from other sequential instructions, or depends on other instructions for its execution. After this, the microprocessor then deploys several execution units to implement two or more separate instructions at a time.
A superscalar architecture, among other things, allows faster-processing speed than would be otherwise obtainable at a given clock rate. It implements more than one instruction during a clock cycle by delegating multiple instructions to other functional units on the computer’s processor. And it does so concurrently. It has the following features.
First, commands are received from a sequential stream of instructions. Secondly, the central processing unit intelligently scouts for possible dependencies between the data and the instructions issued at run time. Thirdly, the central processing unit can implement multiple instructions in each clock cycle.
At their core pipelining and superscalar architecture are both pipelined. However, pipelining and superscalar execution are different systems for speedy performance. While the superscalar architecture implements multiple instructions simultaneously through multiple execution units, pipelining architecture implements multiple commands or instructions in a similar execution unit by splitting the execution unit into different sections or phases.
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